No idea of release dates or price, but would present some kind of breakthrough
10 to 25x increase in energy efficiency for the same performance level compared to existing GPU and CPU systems
256 CORES PER CHIP, SCRATCHPAD MEMORY, A 2D-MESH INTERCONNECT, AND A REVOLUTIONARY HIGH BANDWIDTH CHIP-TO-CHIP INTERCONNECT ACHIEVE:
256 GFLOPs DP or 512 GFLOPs SP at 64 to 128 GFLOPs/watt
- Same performance for integer calculations.
- Balanced memory bandwidth allows near-theoretical peak performance.
- Extreme scalability: near limitless number of Neo chips per node.
Hardware/Software codesign is a crucial component of the Neo architecture, and specific emphasis was given to give programmers both development ease and low-level access to the hardware to maximize efficiency and performance.
- Neo cores are capable of running a minimal Linux environment.
- Targeting the MIMD Neo architecture can be as simple as
cross-compiling existing code.
PERFORMANCE TUNING SUITE
- Compiler support for advanced automatic scratchpad management
(integrated with GCC and LLVM).
- Code profiling tools enable evidence-driven optimization.
COMPLETE CONTROL OVER HARDWARE
Optional access to unique features, including explicit data flow management and static scheduling.